Resources Category: Brochure

The complexity of the electrical system in today’s cars and commercial vehicles has increased tremendously over the last few decades. The expansion of infotainment and the addition of numerous safety systems has multiplied the number of wires and so is the case with aerospace and industrial applications. The move to hybrid and electric motors introduced high voltage to a low voltage environment. To add to this, the ongoing development of vehicle platforms is shared and designed by teams across the world. These factors result in huge and complex designs that need to be designed efficiently and verified quickly and reliably. Design teams working on these platforms are under constant pressure to reduce the cost of the design and improve the design process. These challenges are universal for the development of all electrical systems.

Silver is a Software-in-the-Loop (SiL) solution to create and run virtual ECUs (vECUs). It provides an early, scalable, cost-effective, and deterministic simulation platform for ECU development, functional test, and validation. Increasing software complexity further delays the availability of ECUs due to larger and time-consuming iteration cycles. Automotive manufacturers need to test their ECUs as early as possible, ideally before HW is available to meet aggressive time-to-market schedules and with that, reduce costs. Virtual ECUs are key to fast feedback loops and thus ensure the quality of complex control software.

Synopsys Saber is a solution of high-precision virtual prototyping tools for multi-domain power electronics design that consists of SaberEXP, SaberRD, and SaberES Designer. SaberEXP is a piecewise linear (PWL) quick converging simulator for power electronics, with seamless export into SaberRD. With simplified models and minimal simulator calibration parameters, SaberEXP is easier to use and more robust than SPICE-like tools. It is built from PWL numerical methods for systems without integration error, producing faster results for stiff power electronic circuits in both time and frequency domains.

Synopsys StarRC™, the Gold standard parasitic extraction solution, is a key component of the Synopsys Digital Design and the Synopsys Custom Design Families. Synopsys StarRC provides a silicon-accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal, memory and 3DIC designs. The Synopsys StarRC solution offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16nm, 14nm, 10nm, 7nm, 5nm, 3nm and beyond

The Synopsys PrimePower product family enables accurate power analysis for block-level and full-chip designs starting from RTL, through the different stages of implementation, and leading to power signoff. PrimePower RTL power estimation provides RTL designers with fast, scalable, and accurate power estimation for early analysis of RTL blocks, subsystems, and full-SoCs

Signoff users have a few key requirements for their signoff tool of choice: runtime and capacity to handle their largest chip size requirements, efficient multi-scenario analysis to verify timing across all corners and modes, margin control to reduce over-design and maximize chip performance, and accuracy to ensure correlation to silicon.